PROJECT TITLE :

A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces

ABSTRACT:

Currently, state-of-the-art motor intention decoding algorithms in brain-machine interfaces are principally implemented on a LAPTOP and consume significant quantity of power. A Machine Learning coprocessor in 0.thirty five- μm CMOS for the motor intention decoding within the brain-machine interfaces is presented during this paper. Using Extreme Learning Machine algorithm and low-power analog processing, it achieves an energy potency of 3.forty five pJ/MAC at a classification rate of fifty Hz. The learning in second stage and corresponding digitally stored coefficients are used to increase robustness of the core analog processor. The chip is verified with neural knowledge recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.threepercent for movement type. The same coprocessor is additionally used to decode time of movement from asynchronous neural spikes. With time-delayed feature dimension enhancement, the classification accuracy can be increased by fivepercent with restricted number of input channels. Further, a sparsity promoting training theme allows reduction of number of programmable weights by ≈ 2X.