PROJECT TITLE :

Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

ABSTRACT:

Nonvolatile memory like magnetic RAM (MRAM) offers high cell density and low leakage power whereas plagued by long write latency and high write energy, compared with SRAM. three-D integration technology using through-silicon vias allows stacking disparate memory technologies (e.g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The utilization of hybrid recollections as an on-chip cache will exploit the best characteristics that each technology offers. But, the inherent high power density and warmth removal limitation in 3-D integrated circuits might incur temperature-related issues. In this paper, we tend to propose a runtime thermal management technique for CMPs with the three-D stacked hybrid SRAM/MRAM L2 cache. The proposed methodology combines dynamic cache management like resource allocation, manner-based mostly power gating, and information migration with dynamic voltage and frequency scaling of processing cores in a very temperature- and energy-aware manner. Experimental results show that the proposed runtime technique with the three-D stacked hybrid L2 cache offers up to 107.thirty sevenp.c (55.twenty eightp.c on average) performance improvement and eighty eight.forty sevenpercent (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-d stacked SRAM-based L2 cache.