PROJECT TITLE :

An Inter/Intra-Chip Optical Network for Manycore Processors

ABSTRACT:

Manycore processor system is changing into an enticing platform for applications seeking each high performance and high energy potency. However, huge communication demands among cores, massive power density, and low method yield will be three significant limitations for the scalability of future manycore processors. Breaking a massive chip into multiple smaller ones will alleviate the issues of power density and yield, but would worsen the matter of communication efficiency because of the restricted off-chip bandwidth. In response, we have a tendency to propose an inter/intra-chip optical network, that will not solely fulfill the intra-chip communication necessities however also address the inter-chip communication, by exploiting the advantages of optical links with high bandwidth and energy potency. The network consists of an inter-chip subnetwork and multiple intra-chip subnetworks, and therefore the subnetworks closely coordinate with each different to balance the traffic. The proposed network effectively explores the distinctive properties of optical signals and photonic devices, and dynamically partitions every data channel into multiple sections. Each section can be utilised independently to boost performance as well as cut back energy consumption. Simulation results show that our network can achieve higher throughput with lower power consumption than different styles below most of artificial traffics and real applications.