A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel

PROJECT TITLE :

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel

ABSTRACT:

A sixteen.8 Gbps/channel single-ended transceiver for SiP-based mostly DRAM interface on silicon carrier channel is proposed in this paper. A transmitter, receiver, and channel are all included during a single package as SiP. A current mode 4:1 MUX with 1-tap feed-forward equalizer (FFE) is used as a serializer, and this 4:1 MUX uses 25p.c duty clock to forestall short circuit current when consecutive 2-phase clocks overlap. Additionally, an open drain output driver with asynchronous sort one-faucet FFE is employed in the transmitter. As a result of of its tiny physical size, a standard mode variation of Si-carrier channel from method variation is more serious than that of conventional PCB. This common mode variation degrades bit error rates (BER) at single-ended signaling. To obtain effective single-ended signaling on Si-carrier channel, a source follower-based mostly continuous time linear equalizers and self- VREF generator with coaching algorithm on the receiver are proposed. An implemented Si-carrier channel uses meshed layer as a reference to reduce insertion loss. A BER less than 1e-12 is achieved in sixty five nm CMOS and the ability efficiency of the transceiver is 5.9 pJ/bit with a hundred and twenty Ω terminations at every transceiver side.

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