PROJECT TITLE :
A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads
To guard multicores from soft-error perturbations, resiliency schemes have been developed with high coverage however high power/performance overheads (~2x). We tend to observe that not all soft-errors have an effect on program correctness, some soft-errors only have an effect on program accuracy, i.e., the program completes with sure acceptable deviations from soft-error free outcome. So, it's sensible to enhance processor efficiency by trading off resilience overheads with program accuracy. We tend to propose the idea of declarative resilience that selectively applies resilience schemes to both crucial and non-crucial code, while making certain program correctness. At the application level, crucial and non-crucial code is identified based on its impact on the program outcome. The hardware collaborates with software support to enable economical resilience with a hundred % soft-error coverage. Solely program accuracy is compromised within the worst-case situation of a soft-error strike throughout non-crucial code execution. For a set of multithreaded benchmarks, declarative resilience improves completion time by a median of 21 percent over state-of-the-art hardware resilience scheme that protects all executed code. Its performance overhead is ~1.38x over a multicore that does not support resilience.
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