Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor


During this paper, we have a tendency to propose a technique to optimize the product performance instantly by utilizing the inner voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we tend to initial outline the verification wafer as the inner voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a traditional wafer being matched with a verification wafer. The proposed technique makes the flexibility to apply a different voltage trimming condition for every dies internal voltage circuit relying on their characteristics, thereby improving the characteristics of the individual dies and reducing the fail bit count (FBC) more. The experimental results on the real-application case show that our proposed technique reduces the FBC by 1%–five%, that contributes yield enhancement and quality improvement of DRAM memory by raising the potency of the redundancy cell repair within the repair method.

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