PROJECT TITLE :
Investigation of Low-Frequency Noise in Nonvolatile Memory Composed of a Gate- All-Around Junctionless Nanowire FET
Low-frequency noise (LFN) behaviors, characterised with an SONOS-primarily based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this sort of NW as a memory cell structure. LFN exhibits a 1/ -form and is described by a carrier number fluctuation noise model. It's found that the proposed device structure shows a coffee level of device-to-device variation and high immunity against Fowler–Nordheim tunneling stress. Due to the targeted conduction path within the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge within the nitride layer of the Silicon(Poly-Si)-oxide(SiO2)-nitride(SiNx)-oxide(SiO2)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and supply/drain series resistance below a recent and a programmed state.
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