Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs


Large temperature gradients exacerbate varied varieties of defects including early-life failures and delay faults. Efficient detection of those defects needs that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is abundant more vital for 3-D stacked ICs (three-D SICs) compared with 2-D ICs as a result of of the larger temperature gradients in three-D SICs. During this paper, two strategies to efficiently enforce the required temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high-power stimuli to the cores of the IC beneath take a look at through the take a look at access mechanism. So, no external heating mechanism is needed. The tests, high power stimuli, and cooling intervals are scheduled together primarily based on temperature simulations therefore that the specified temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. The experimental results demonstrate the potency of the proposed methods.

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