Low-cost high-efficiency solar cells are the key to achieve grid parity with photovoltaic devices. High-quality rear passivation is essential for the achievement of this goal. Thick thermal oxide is known to provide the required back surface passivation, but it can lead to long process steps at a high temperature. A combination of 2-D simulations and experiments is used to identify a dielectric stack that provides passivation comparable with that of a thick thermal oxide. This dielectric stack, in conjunction with a local back surface field and 75- Ω/sq emitter, produced solar cell efficiency exceeding 20%. In addition, a streamlined process sequence, involving a single high temperature step for simultaneous formation of emitter and rear passivation, is used. The peak efficiency of 20.1% was achieved with J $_{rm SC}$ of 39.4 mA/cm$^2$ and V$_{rm OC}$ of 652 mV on float zone wafers of 2.3 Ω·cm resistivity. Detailed characterization and modeling revealed that the increase in V$_{rm OC}$ and J$_{rm SC}$ is the result of increased back surface reflectance from 67% to 93% and reduced back surface recombination velocity from 325 to 125 cm/s. Improved rear passivation was found to be an effective method to control charge-induced inversion or parasitic shunting at the rear surface. According to model calculations, further optimization can result in efficiencies of over 20% on much thinner wafers (∼100 μm) using an identical cell structure.

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