Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability


During this paper, we have a tendency to present a variability-aware three-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire MOSFET (NWFET)-primarily based six-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected space temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET vi-T SRAM cell with VDD downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with VDD downscaling, kind of like the hold SNM experimental information reported in the literature for Si GAA NWFET-primarily based SRAM arrays. We more show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.

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