PROJECT TITLE :
A 4.5 mW CT Self-Coupled Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation
This paper presents an influence-efficient single-loop continuous-time (CT) $DeltaSigma$ modulator (DSM) that achieves a SNDR of 90.4 dB over a two.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward design incorporating the continual-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a very 55 nm LP CMOS technology. Operating at a hundred and forty MHz sampling rate, the chip consumes four.five mW from power provides of 1.a pair of V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a two.two MHz signal bandwidth, ensuing in a very Schreier FOM of 17seven.3 dB and 178.9 dB primarily based on SNDR and DR, respectively. The chip space is 0.09 mm$^2$.
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