Adapting Interconnect Technology to Multigate Transistors for Optimum Performance


Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Therefore, the main target is on optimizing interconnect parasitics so as to achieve optimum performance. The increased total device capacitance and therefore the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. During this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and fewer aggressive wire width and thickness scaling are proposed. This analysis is dole out primarily based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed very well. This approach compromises wire capacitance and gradually renders it necessary in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the ancient BEOL scaling versus the proposed wire sizing. It's found that using the latter wire sizing approach with air-gap interconnects is additional beneficial to circuit performance.

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