PC-TRIO: A Power Efficient TCAM Architecture for Packet Classifiers PROJECT TITLE :PC-TRIO: A Power Efficient TCAM Architecture for Packet ClassifiersABSTRACT:PC-TRIO is an indexed TCAM design for packet classification. In addition to index TCAMs, PC-TRIO uses wide SRAM words. On our packet classifier information sets, PC-TRIO reduced TCAM power by ninety six percent and lookup time by 98 % on a mean, compared to PC-DUOS+ [twenty eight] that doesn't use indexing or wide SRAMs. PC-DUOS+ was shown to be better than STCAM, which is a single TCAM architecture conventionally used for packet classification [twenty eight]. In this paper, we have a tendency to conjointly extend PC-DUOS+ by augmenting it with wide SRAMs and index TCAMs using the same methodology as used in PC-TRIO, to obtain PC-DUOS+W. On ACL information sets, PC-DUOS+W reduced TCAM power by eighty six % and lookup time by ninety eight percent, compared to PC-DUOS+, that demonstrates the effectiveness of indexing and usage of wide SRAMs in reducing power and lookup time for packet classifiers. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Aerospace electronics enthusiasts Storage Placement in Path Networks
