Manufacturing Yield for Multiple Lines Gold Bumping Processes With Asymmetric Tolerances


Development of bit show driver IC (TDDI) has enabled slimmer smartphone design by virtue of the mixing of bit controller and display driver ICs (DDIs) into one chip. TDDI plays an necessary role in touch integrated display panels. Compared to conventional DDI, TDDI needs a lot of bonding pads for touch applications, therefore increasing the usage of gold. The requirement to keep costs down forces manufacturers to seem for ways in which to scale back the usage of gold. So as to cut back the usage of gold, gold bumping processes with asymmetric tolerances are thought-about, in which deviations from the target are less tolerable in lower specification limits than in upper specification limits. Additionally, thanks to economies of scale issues, gold bumping processes involving multiple manufacturing lines are commonly thought-about in Taiwan. However, no yield index has been developed for multiple-line gold bumping processes with uneven tolerances. In this paper, we have a tendency to propose a replacement yield index and derive an approximate distribution of . In addition, the lower confidence bounds and vital values are provided for the multiple-line gold bumping processes with asymmetric tolerances. For illustration functions, a real-world application in a gold bumping factory that is located in the Science-Based mostly Industrial Park in Hsinchu, Taiwan, is presented.

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