Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge PROJECT TITLE :Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy BridgeABSTRACT:Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach that's adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intel's Sandy Bridge microprocessor. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Sparc T4: A Dynamically Threaded Server-on-a-Chip AMD Fusion APU: Llano
