Design Architecture of a 2-D Separable Iterative Soft-Output Viterbi Detector


Viterbi detectors are widely utilized in all Communication systems addressing transmission and storage. During this paper, we develop the theory and design architecture for a two-D separable iterative soft-output Viterbi detector (SISOVD) for applications in a pair of-D storage channels extending the first work from Wu et al. (IEEE Trans. Magn., vol. 39, no. four, pp. 2115–2120, Jul. 2003). The contribution of this paper is twofold. First, we have a tendency to design a non-binary soft Viterbi detector that can be used because the core engine for the SISOVD and show its equivalence to the max-log-MAP algorithm implementation. We tend to conjointly study the performance of the algorithm through simulations underneath various style parameter constraints toward a systems design. Second, we tend to propose a unique digital circuit that comes with non-uniform quantization inside a sliding block style framework. The proposed detector system architecture is tested within an field programmable gate array platform and proved to be efficient in terms of resource utilization, timing, and power compared with a standard uniform quantizer with no signal-to-noise ratio performance degradation. It shows a thirteen.twenty eight% reduction in the full variety of slice registers, thirty.26% reduction in the slice lookup tables, 21.twenty three% reduction in the crucial path delay, and 14.84% reduction in the power consumption compared with the uniform quantizer.

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