PROJECT TITLE :

A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA - 2017

ABSTRACT:

Thanks to the traditional look-up-table (LUT) using the static random access memory (SRAM) cell, field programmable gate arrays (FPGAs) virtually reach the limitation in term of the density, speed, and configuration overhead. This paper proposes an improved memristor-based mostly LUT (MLUT) circuit which is compatible with the mainstream LUT circuit in FPGA. Any arbitrary combined logic functions can be implemented within the MLUT through specific configurations. Then the MLUT shows superior advantages over the conventional LUT like smaller area overhead and fewer information transmission. As a case study, a one-bit full adder is simulated to verify that the planning is of follow in PSPICE. Moreover, the adder can be cascaded into multibit full adder demonstrating competitiveness against the traditional configurable logic block in FPGA technology. MLUT can be a candidate to switch the standard SRAM-primarily based LUT and more improves the performance of FPGAs.