A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier

Email Usinfo@mtechprojects.com
Phone Number+91 9573777164
Open Hours9 am - 6 pm / Mon - Sat

Details: Category: MTech VLSI Projects; By MTech Projects; 11.Oct; Hits: 14

PROJECT TITLE :

A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier - 2018

ABSTRACT:

A thirty two-bit 4 × four bit-slice fast single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a sixteen-bit bit-slice processing has the least latency at ten GHz.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-like Block Ciphers - 2017
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication - 2015
A New XOR-Free Approach for Implementation of Convolutional Encoder - 2016
Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic - 2018
A Modified Partial Product Generator for Redundant Binary Multipliers - 2016
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding - 2017
Digtial to time converter using SET - 2015
Voltage mode implementation of highly accurate analog multiplier circuit - 2015
A Low Power Reconfigurable LFSR - 2016
A Modified Partial Product Generator for Redundant Binary Multipliers - 2016

VLSI Core MTech Projects

Contact Us