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  4. High Performance Complex Number Multiplier Using Booth-Wallace Algorithm
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Category: MTech VLSI Projects
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MTech Projects
26.Jun
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High Performance Complex Number Multiplier Using Booth-Wallace Algorithm

High Performance Complex Number Multiplier Using Booth-Wallace Algorithm

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  • Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
  • High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors - 2015
  • Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST - 2016
  • A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits
  • A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling - 2016
  • A Modified Partial Product Generator for Redundant Binary Multipliers - 2016
  • Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment - 2015
  • Digtial to time converter using SET - 2015
  • A Novel Data Format for Approximate Arithmetic Computing - 2017
  • Floating-Point Butterfly Architecture Based on Binary SignedDigit Representation - 2016
Previous article: Design and Implementation of Lossless DWT/IDWT for Medical Images Design and Implementation of Lossless DWT/IDWT for Medical Images Next article: High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming
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