High Performance Ternary Adder using CNTFET - 2017

Design of Digital FM Receiver using PLL (Phase Locked Loop)

Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications - 2017

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development - 2016

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017

Digitally Controlled Pulse Width Modulator for On-Chip Power Management

A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies - 2016

A novel VHDL implementation of UART with single error correction and double error detection capability - 2015

Self-Immunity Technique to Improve Register File Integrity against Soft Errors