PROJECT TITLE :

A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography - 2016

ABSTRACT:

This paper presents a fixed-purpose reconfigurable parallel VLSI hardware design for real-time Electrical Capacitance Tomography (ECT). It is modular and consists of a front-end module that performs precise capacitance measurements in an exceedingly time multiplexed manner using Capacitance to Digital Converter (CDC) technique. Another FPGA module performs the inverse steps of the tomography algorithm. A twin port designed-in memory banks store the sensitivity matrix, the particular worth of the capacitances, and the particular image. A two dimensional (2D) core multi-processing components (PE) engine inter-communicates with these memory banks via parallel buses. A Hardware-software codesign methodology was conducted using commercially offered tools in order to concurrently tune the algorithms and hardware parameters. Hence, the hardware was designed right down to the bit-level in order to scale back both the hardware value and power consumption, whereas satisfying real-time constraint. Quantization errors were assessed against the image quality and bit-level simulations demonstrate the correctness of the planning. Additional simulations indicate that the proposed architecture achieves a speed-up of up to three orders of magnitude over the software version when the reconstruction algorithm runs on 2.53 GHz-primarily based Pentium processor or DSP Ti's Delphino TMS320F32837 processor. A lot of specifically, a throughput of seventeen.241 Kframes/sec for each the Linear-Back Projection (LBP) and modified Landweber algorithms and 8.475 Kframes/sec for the Landweber algorithm with 200 iterations could be achieved. This performance was achieved using an array of [2 x 2] x [two x a pair of] processing units. This satisfies the important-time constraint of many industrial applications. To the best of the authors' knowledge, this is the first embedded system which explores the intrinsic parallelism which is available in trendy FPGA for ECT tomography.