PROJECT TITLE :
Area-time Efficient Architecture of FFT-based Montgomery Multiplication - 2017
The modular multiplication operation is the most time-consuming operation for number-theoretic cryptographic algorithms involving large integers, such as RSA and Diffie-Hellman. Implementations reveal that more than 75 % of the time is spent within the modular multiplication operate among the RSA for a lot of than 1,024-bit moduli. There are quick multiplier architectures to attenuate the delay and increase the throughput using parallelism and pipelining. However such styles are massive in terms of space and low in potency. During this paper, we tend to integrate the fast Fourier rework (FFT) methodology into the McLaughlin's framework, and gift an improved FFT-based mostly Montgomery modular multiplication (MMM) algorithm achieving high area-time efficiency. Compared to the previous FFT-primarily based designs, we inhibit the zero-padding operation by computing the modular multiplication steps directly using cyclic and nega-cyclic convolutions. Thus, we cut back the convolution length by half. Furthermore, supported by the amount-theoretic weighted remodel, the FFT algorithm is employed to provide quick convolution computation. We tend to additionally introduce a general methodology for economical parameter choice for the proposed algorithm. Architectures with single and double butterfly structures are designed obtaining low area-latency solutions, which we implemented on Xilinx Virtex-half-dozen FPGAs. The results show that our work offers a better space-latency potency compared to the state-of-the-art FFT-primarily based MMM architectures from and on top of one,024-bit operand sizes. We have obtained space-latency potency improvements up to fifty.9 p.c for 1,024-bit, forty one.nine percent for two,048-bit, 37.eight p.c for four,096-bit and 103.a pair of p.c for 7,680-bit operands. Furthermore, the operating latency is also outperformed with high clock frequency for length-sixty four transform and higher than.
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