PROJECT TITLE :
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity - 2017
The planning of high-performance adders has experienced a renewed interest in the previous couple of years; among high performance schemes, parallel prefix adders constitute an necessary category. They need a logarithmic range of stages and are typically realized using AND-OR logic; moreover with the emergence of recent device technologies based on majority logic, new and improved adder styles are attainable. But, the simplest existing majority gate-primarily based prefix adder incurs a delay of 2log2(n) - one (due to the nth carry); this is often only marginally higher than a style using only AND-OR gates (the latter design incorporates a 2log2(n) + 1 gate delay). This paper initially shows that this delay is caused by the output carry equation in majority gate-primarily based adders that's still largely defined in terms of AND-OR gates. During this paper, two new majority gate-primarily based recursive techniques are proposed. The first technique depends on a unique formulation of the bulk gate-based mostly equations in the used group generate and cluster propagate hardware; this leads to a brand new definition for the output carry, thus reducing the delay. The second contribution of this manuscript utilizes recursive properties of majority gates (through a unique operator) to cut back the circuit complexity of prefix adder designs. Overall, the proposed techniques lead to the calculation of the output carry of an n-bit adder with only a majority gate delay of log2 (n) + one. This results in a discount of 40percent in delay and 30percent in circuit complexity (in terms of the amount of majority gates) for multi-bit addition as compared to the best existing styles found within the technical literature.
Did you like this research project?
To get this research project Guidelines, Training and Code... Click Here