A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits - 2016


Minimization of power dissipation of VLSI circuits is one amongst the main concerns of recent digital circuit design primarily thanks to the ever decreasing feature sizes of circuits, higher clock frequencies and bigger die sizes. The primary contributors to power dissipation in digital circuits embrace leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the most important component. As such, a good mechanism to reduce the ability loss in such cases usually involves the minimization of the switching activity. During this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and also the results obtained are quite encouraging.

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