PROJECT TITLE :
A High Throughput List Decoder Architecturefor Polar Codes - 2016
While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels when decoded by a coffee complexity successive-cancellation (SC) algorithm, the error performance of the SC algorithm is inferior for polar codes with finite block lengths. The cyclic redundancy check (CRC)-aided SC list (SCL) decoding algorithm has higher error performance than the SC algorithm. However, current CRC-aided SCL decoders still suffer from long decoding latency and limited throughput. In this paper, a reduced latency list decoding (RLLD) algorithm for polar codes is proposed. Our RLLD algorithm performs the list decoding on a binary tree, whose leaves correspond to the bits of a polar code. In existing SCL decoding algorithms, all the nodes within the tree are traversed, and every one possibilities of the data bits are thought-about. Instead, our RLLD algorithm visits abundant fewer nodes in the tree and considers fewer possibilities of the information bits. When configured properly, our RLLD algorithm considerably reduces the decoding latency and, hence, improves throughput, while introducing very little performance degradation. Based mostly on our RLLD algorithm, we conjointly propose a high throughput list decoder design, that is appropriate for larger block lengths because of its scalable partial sum computation unit. Our decoder design has been implemented for various block lengths and list sizes using the TSMC ninety-nm CMOS technology. The implementation results demonstrate that our decoders achieve vital latency reduction and space efficiency improvement compared with the opposite list polar decoders within the literature.
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