A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process - 2015
In this project, we present one-bit clock-less asynchronous delta-sigma modulator (ADSM) operating at just 0.twenty five V power offer. Several circuit approaches were utilized to enable such low-voltage operation and maintain high performance. One approach concerned utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the impact of low output impedance because of halo drain implants utilized in nowadays's digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of fifty eight dB or effective variety of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the impact of nonidealities of the individual circuit parts is also presented for the primary time with a close agreement with experimental results.
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