Glitch free combinational clock gating approach in nanometer VLSI circuits - 2015
Low power design is gaining prominence because of the increasing would like of battery operated portable devices with high computing capability. It is the essential issue in ASIC style, as featured size is scaled down. The reliability of integrated circuit depends on the heat dissipated within the circuit. A massive fraction of the facility consumed is due to the clock distribution network and also the high switching activity at the nodes. Clock Gating is the well-known power-saving technique used to cut back the clock power. To save power, clock gating refers to triggering the clocks in a logic block only when there is work to be done. Every unit on the chip incorporates a power reduction plan, and nearly every Functional Unit Block (FUB) contains clock gating logic. During this project, we have a tendency to justify the method of Glitch reduction for ISCAS 85 bench mark circuits using combinational clock gating principle. The functionality of bench mark circuits are verified using Cadence physical flow with RTL compiler.
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