High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis - 2015
Image scaling may be a fundamental algorithm employed in a large range of digital image applications. In this project, we propose an economical VLSI architecture for a novel edge-directed linear interpolation algorithm. Our VLSI design is implemented using high level synthesis (HLS) tool, which generates RTL modules from C/C++ functions. HLS provides significantly improved style productivity compared to the ancient RTL-based mostly style flow. Thus we have a tendency to explored a massive style area including several fine-grained and coarse-grained optimizations within the pipeline design design. Our architecture is verified in an exceedingly working system based mostly on Xilinx Kintex-7 FPGA. Experiments show that our design will process UHD (3840*2160) videos at 30fps with moderate resource utilization.
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