Quaternary Logic Lookup Table in Standard CMOS - 2015
Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic will decrease the common power required for level transitions and reduces the amount of required interconnections, hence conjointly reducing the impact of interconnections on overall energy consumption. During this project, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with normal CMOS processes, with one voltage provide and employing only simple voltagemode structures. A clock boosting technique is employed to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations revealed so far, like the necessity for special options within the CMOS method or power-hungry current-mode cells. We tend to present a full adder prototype primarily based on the designed LUT, fabricated in a very standard 130-nm CMOS technology, in a position to figure at one hundred MHz whereas consuming twelvea pair of µW. The experimental results demonstrate the proper quaternary operation and ensure the power efficiency of the proposed design.
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