A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) - 2015 PROJECT TITLE: A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) - 2015 ABSTRACT: This project presents a unique low-complexity cross parity code, with a big selection of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme will correct m = Dw = 3m/two -one multiple error mixtures out of all the attainable 2m - 1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on eighty-bit parallel and, for the first time, on 163-bit Federal Data Processing Customary/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and a hundred and seventypercent space overheads, respectively, that is not up to the present approaches, whereas error injection-based mostly behavioral analysis demonstrates its wider error correction capability. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A novel VHDL implementation of UART with single error correction and double error detection capability - 2015 A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning - 2015
