A novel VHDL implementation of UART with single error correction and double error detection capability - 2015
In an industrial working environment using multiprocessor communication using UART, noise is seemingly to have an effect on the info and data might be received with errors. This reasonably error incidence could affect the operating of the system ensuing in an improper control. Many existing UART designs are incorporating error detection logic. This reasonably logic, if detects errors, needs retransmission of corresponding information frames that take additional time for automatic repeat request (ARQ) and retransmission of knowledge. Linear block codes like hamming code have forward error correction (FEC) with error detection capability. This project presents a completely unique VLSI implementation of UART designed to include (8,4) extended hamming code referred to as SEC-DED code that may correct upto one error and detect upto 2 errors. This improves the noise immunity of the system optimizing the error free reception of information. The whole style is implemented in Xilinx ISE twelve.3 simulator targeted to Xilinx Spartan 6 FPGA.
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