A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply - 2016
This project presents a new power-efficient electrocardiogram acquisition system that uses a fully digital design to cut back the facility consumption and chip space. The proposed architecture is compatible with digital CMOS technology and is capable of operating with a low provide voltage of zero.five V. During this design, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive parts, like ac coupling capacitors, are used. A moving average voltage-to-time converter is used, which behaves rather than the LNA and antialiasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, that eliminates the requirement for coupling capacitors. The circuit is implemented in zero.18-um CMOS method. The simulation results show that the front-end circuit consumes 274 nW of power.
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