Design and implementation of fast floating point multiplier unit - 2015


Floating purpose numbers are the quantities that cannot be represented by integers, either because they contain fractional values or as a result of they lie outside the vary re presentable within the system's bit width. Multiplication of two floating point numbers is very vital for processors. Architecture for a quick floating purpose multiplier yielding with the only precision IEEE 754-2008 customary has been utilized in this project. The floating point representation can preserve the resolution and accuracy compared to mounted point. Pipeline could be a technique where multiple directions are overlapped in execution. Multiple operations performed at the identical time by pipeline will increase the instruction throughput. In many high performance computing systems such as digital signal processors, FIR filters, microprocessors, etc multipliers are key parts. The foremost vital aim of the look is to form the multiplier quicker by decreasing delay. Decrease of delay can be caused by propagation of carry within the adders having smallest amount power delay constant.

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