PROJECT TITLE:

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic - 2015

ABSTRACT:

Digital multipliers are among the most critical arithmetic purposeful units. The performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability impact happens when a pMOS transistor is under negative bias (Vgs = -Vdd), increasing the brink voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system might fail because of timing violations. Thus, it's important to design reliable high-performance multipliers. In this project, we have a tendency to propose an aging-aware multiplier style with a unique adaptive hold logic (AHL) circuit. The multiplier is in a position to provide higher throughput through the variable latency and will regulate the AHL circuit to mitigate performance degradation that is because of the aging impact. Moreover, the proposed architecture can be applied to a columnor row-bypassing multiplier. The experimental results show that our proposed design with 16 × sixteen and 32 × thirty two column-bypassing multipliers can attain up to sixty two.88percent and seventy six.28p.c performance improvement, respectively, compared with 16×sixteen and 32×32 fastened-latency column-bypassing multipliers. Furthermore, our proposed architecture with sixteen × 16 and thirty two × 32 row-bypassing multipliers will achieve up to 80.17p.c and 69.fortypercent performance improvement as compared with 16×16 and thirty two × 32 fastened-latency row-bypassing multipliers.


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