Design and FPGA implementation of compressor based Vedic multiplier - 2014


Multiplier is one vital block in digital signal processor, pc, etc. In this project, a novel high speed adder primarily based compressor has been proposed. Earlier version of computational systems such multipliers, parallel adders and serial adders utilized 0.5 adder and full adders for binary addition. [*fr1] adder and full adder are capable of adding a pair of and 3-bits respectively. To perform a lot of than 3-bit addition, either goes to serial or parallel adder. This might yield high area and high propagation delay-time.

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