Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code - 2014
Transient multiple cell upsets (MCUs) are becoming major problems in the reliability of reminiscences exposed to radiation setting. To forestall MCUs from inflicting information corruption, a lot of advanced error correction codes (ECCs) are widely used to guard memory, but the most problem is that they might require higher delay overhead. Recently, matrix codes (MCs) primarily based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and also the error correction capabilities don't seem to be improved in all cases. In this project, novel decimal matrix code (DMC) based on divide-image is proposed to boost memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the most error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to reduce the realm overhead of additional circuits while not disturbing the entire encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed DMC is compared to well-known codes such as the present Hamming, MCs, and punctured distinction set (PDS) codes. The obtained results show that the mean time to failure (MTTF) of the proposed scheme is 452.9percent, 154.half dozenp.c, and 122.half-dozen% of Hamming, MC, and PDS, respectively. At the identical time, the delay overhead of the proposed theme is 73.1p.c, sixty nine.0p.c, and twenty six.2% of Hamming, MC, and PDS, respectively. The solely downside to the proposed theme is that it needs a lot of redundant bits for memory protection.
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