A New VLSI Architecture Of Parallel Multiplier Accumulator Based On Radix-2 Modified Booth Algorithm. ABSTRACT: With the recent fast advances in multimedia and Communication systems, real-time Signal Processing like audio Signal Processing, video/Image Processing, or giant-capability data processing are increasingly being demanded. The multiplier and multiplier-and-accumulator (MAC) are the essential parts of the Digital Signal Processing like filtering, convolution, and Inner products. In this project, I proposed a replacement architecture of multiplier-and-accumulator (MAC) for top-speed arithmetic. By combining multiplication with accumulation and devising a hybrid kind of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the general performance was elevated. The proposed CSA tree uses 1’s-complement-based mostly radix-2 changed Booth’s algorithm (MBA) and has the changed array for the sign extension in order to extend the bit density of the operands. The CSA propagates the carries to the least vital bits of the partial product and generates the least important bits beforehand to decrease the quantity of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate leads to the type of add and carry bits instead of the output of the final adder, that made it doable to optimize the pipeline scheme to boost the performance. In this project for simulation we use Modelsim for logical verification, and any synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification on targeted FPGA. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Design And Characterization Of Parallel Prefix Adders Using FPGAS An Efficient Architecture For 3-D Discrete Wavelet Transform.