When the DA (distributed arithmetic) algorithm is directly applied in FPGA (field programmable gate array) to understand FIR (finite impulse response) filter, it is difficult to attain the simplest configuration in the coefficient of FIR filter, the storage resource and also the computing speed. According to the present problem, the paper provides the detailed analysis and discussion within the algorithm, the memory size and the design-up table speed. Additionally, the corresponding optimization and improvement measures are discussed and also the concrete hardware realization of the circuit is presented. The results of simulation and check show that this method greatly reduces the FPGA hardware resource and also the high speed filtering is achieved. The look contains a huge breakthrough compared to the traditional FPGA realization.
The sigma-delta modulator based closed loop systems create high resolution, high SNR, low frequency systems. The sigma-delta analog to digital converter consists of the modulator followed by the decimation filter. In this project the planning and FPGA implementation of decimation filter, which performs the action of filtering the shaped quantization noise and changing one-bit data stream into 20 bit high-resolution output is reported.
The multi-stage decimation methodology is customized, with the Cascaded Integrator Comb (CIC) filter followed by a FIR filters. The specifications of decimation filter are derived from the specifications of a 3rd-order single bit sigma-delta modulator. Distributed arithmetic algorithm is employed to design FIR filters. The hardware model for the filter is developed using verilog HDL
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