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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. On the Design of Efficient Modulo 2n+1 Multiply Add Add Units - 2014
Details
Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
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On the Design of Efficient Modulo 2n+1 Multiply Add Add Units - 2014

PROJECT TITLE:

On the Design of Efficient Modulo 2n+1 Multiply Add Add Units - 2014

ABSTRACT:

In this work efficient modulo 2n+1 fused multiply-add-add units for weighted and diminished-one operands are proposed. The proposed architectures can be applied in systems in that fused multiply-add-add units accelerate the execution of the targeting algorithms. Long integer arithmetic would also show considerable gains by using multiply-add-add units. Conjointly, implementation results for the proposed units are given and compared to the performance of existing designs.

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