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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. Low Power Test Generation by Merging of Functional Broadside Test Cubes - 2014
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
Hits: 11

Low Power Test Generation by Merging of Functional Broadside Test Cubes - 2014

PROJECT TITLE:

Low Power Test Generation by Merging of Functional Broadside Test Cubes - 2014

ABSTRACT:

This project describes an occasional-power check generation procedure, that targets the switching activity during the quick useful clock cycles of broadside tests. The procedure is predicated on merging of take a look at cubes that it extracts from useful broadside tests. The use of check cube merging supports test compaction and it can be used for accommodating the constraints of test information compression. The employment of useful broadside tests provides a target for the switching activity of low-power tests, that does not exceed the switching activity that's possible throughout practical operation, or that the circuit is intended for. The employment of check cubes that are extracted from functional broadside tests may be a distinctive feature of this procedure. It ensures that the low-power tests would create purposeful operation conditions in subcircuits that are outlined by the take a look at cubes. Experimental results show that the procedure detects all or virtually all the transition faults that are detectable by arbitrary (purposeful and nonfunctional) broadside tests in benchmark circuits.

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