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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
07.Apr
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Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip

PROJECT TITLE :

Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip (2014)

ABSTRACT :

As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we present a set of data encoding schemes aimed at reducing the power dissipated by the links of an NoC. The proposed schemes are general and transparent with respect to the underlying NoC fabric (i.e., their application does not require any modification of the routers and link architecture). Experiments carried out on both synthetic and real traffic scenarios show the effectiveness of the proposed schemes, which allow to save up to 51% of power dissipation and 14% of energy consumption without any significant performance degradation and with less than 15% area overhead in the NI.

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