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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. A Modified Partial Product Generator for Redundant Binary Multipliers - 2016
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
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A Modified Partial Product Generator for Redundant Binary Multipliers - 2016

PROJECT TITLE:

A Modified Partial Product Generator for Redundant Binary Multipliers - 2016

ABSTRACT:

Because of its high modularity and carry-free addition, a redundant binary (RB) representation will be used when planning high performance multipliers. The standard RB multiplier requires a further RB partial product (RBPP) row, as a result of a blunder-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and also the RB encoding. This incurs in an extra RBPP accumulation stage for the MBE multiplier. In this project, a replacement RB changed partial product generator (RBMPPG) is proposed; it removes the additional ECW and hence, it saves one RBPP accumulation stage. Thus, the proposed RBMPPG generates fewer partial product rows than a typical RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs considerably improve the realm and power consumption when the word length of every operand within the multiplier is at least 32 bits; these reductions over previous NB multiplier styles incur in a very modest delay increase (approximately five p.c). The power-delay product will be reduced by up to 59 % using the proposed RB multipliers in comparison with existing RB multipliers.

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Previous article: Design and Analysis of Approximate Compressors for Multiplication - 2015 Design and Analysis of Approximate Compressors for Multiplication - 2015 Next article: Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic - 2015 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic - 2015
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