Algorithm and Architecture for a Low-PowerContent-Addressable Memory Basedon Sparse Clustered Networks - 2015 PROJECT TITLE: Algorithm and Architecture for a Low-PowerContent-Addressable Memory Basedon Sparse Clustered Networks - 2015 ABSTRACT: We propose a coffee-power content-addressable memory (CAM) using a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed design is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed throughout a probe. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes some possibilities for the location of the matched tag and performs the comparisons on them to find a single valid match. TSMC 65-nm CMOS technology was used for simulation purposes. Following a choice of style parameters, such as the number of CAM entries, the energy consumption and also the search delay of the proposed style are eightp.c, and 26percent of that of the conventional NAND design, respectively, with a 10percent area overhead. A style methodology primarily based on the silicon area and power budgets, and performance necessities is mentioned. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary CommonSub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis. - 2015 Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic - 2015
