Test Versus Security Past and Present - 2014
Cryptographic circuits want to be protected against aspect-channel attacks, that target their physical attributes while the cryptographic algorithm is in execution. There can be numerous facet-channels, like power, timing, electromagnetic radiation, fault response, and so on. One such vital facet-channel is the design-for-testability (DfT) infrastructure present for effective and timely testing of VLSI circuits. The attacker will extract secret information stored on the chip by scanning out take a look at responses against some chosen plaintext inputs. The purpose of this project is to initial gift an in depth survey on the state-of-the-art in scan-primarily based side-channel attacks on symmetric and public-key cryptographic hardware implementations, each within the absence and presence of advanced DfT structures, such as take a look at compression and X-masking, which could create the attack difficult. Then, the prevailing scan attack countermeasures are evaluated for determining their security against known scan attacks. In addition, JTAG vulnerability and security countermeasures also are analyzed as part of the external test interface. A comparative space-timing-security analysis of existing countermeasures at numerous abstraction levels is presented in order to assist an embedded security designer build an informed selection for his intended application.
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