Design and Implementation of the Ascend Secure Processor - 2017

PROJECT TITLE :

Design and Implementation of the Ascend Secure Processor - 2017

ABSTRACT:

This paper presents hardware implementations of the Ascend secure processor, prototyped on an FPGA and taped out in a very thirty two nm SOI method. Ascend prevents data leakage over a processor’s digital I/O pins — in explicit, the processor’s requests to external memory — and certifies the program’s execution by integrity-verifying the external memory. In secure processor style, encrypting main memory isn't sufficient for security because where and when memory is accessed reveals secret information. To the current end, Ascend is supplied with a hardware Oblivious RAM (ORAM) controller, which obfuscates the address bus by reshuffling memory as it is accessed. To our data, Ascend is the first prototyping of ORAM in custom silicon. Ascend has additionally been carefully built to ensure its timing behaviors are independent of user non-public information. We describe our open-supply FPGA prototype and the various style issues that were created when optimizing for an FPGA vs. the ASIC. In thirty two nm silicon, all security parts combined (the ORAM controller, that includes 12 AES rounds and one SHA-three hash unit) impose a moderate space overhead of one mm2. Post tape-out, the Ascend chip has been successfully tested at 500 MHz.

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