Scalable GF(p) Montgomery multiplier based on a digit–digit computation approach

PROJECT TITLE :

Scalable GF(p) Montgomery multiplier based on a digit–digit computation approach

ABSTRACT:

This study presents a scalable hardware design for modular multiplication in prime fields GF(p). A completely unique iterative digit-digit Montgomery multiplication (IDDMM) algorithm is proposed and 2 hardware architectures that compute that algorithm are described. The input operands (multiplicand, multiplier and modulus) are represented using as radix β = 2k. Multiplication over GF(p) is potential using almost the same hardware since the complexity of multiplier's kernel module depends mainly on k and not on p. The novel hardware architectures of GF(p) multipliers were evaluated on 3 Xilinx FPGA families. Design trade-offs were analysed considering totally different operand sizes commonly utilized in cryptography and different digits sizes. The proposed styles for IDDMM are compatible to be implemented in fashionable FPGAs, making use of obtainable dedicated multipliers and memory blocks reducing drastically the FPGA's customary logic while keeping an appropriate performance compared with other implementation approaches. From the Virtex5 implementation, the proposed MM multiplier reaches a throughput of 242 Mbps using only 219 FPGA slices and achieving a 1024-bit modular multiplication in four.21μs. This can be 26 times less area resources than similar connected works in the literature with an improved potency of 7x.

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