PROJECT TITLE :

A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

ABSTRACT:

During this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The distinctive properties of VeSFET circuits enable for very economical power saving techniques that are not potential in complementary metal–oxide–semiconductor-primarily based homogeneous 3-D NoCs. We demonstrate that the proposed three-D hybrid architecture shows vital improvements in all network parameters including latency, power, and energy consumption compared to different practical three-D NoCs.