PROJECT TITLE :

Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices

ABSTRACT:

Through-silicon vias (TSVs) have two negative effects in the look of 3-dimensional integrated circuits (three-D ICs). 1st, TSV insertion ends up in silicon space overhead. In addition, nonnegligible TSV capacitance causes delay overhead in three-D signal methods. Thus, getting all benefits like wirelength reduction and performance improvement from three-D ICs is highly enthusiastic about TSV size and capacitance. Meanwhile, TSVs are downscaled to attenuate their negative effects, and sub-micron TSVs are expected to be fabricated within the close to future. At the same time, the devices are downscaled beyond thirty two nm and 22 nm, therefore future three-D ICs will terribly likely be engineered with sub-micron TSVs and advanced device technologies. During this paper, we investigate the impact of sub-micron TSVs on the standard of today and future 3-D ICs. For future process technologies, we tend to develop twenty two nm and 16 nm libraries. Using these future method libraries and an existing forty five nm library, we generate three-D IC layouts with different TSV sizes and capacitances and study the impact of sub-micron TSVs thoroughly.