PROJECT TITLE :
Wire shaping for delay/power minimization has been extensively studied. Because of the perceived high design and producing costs for using nonregular wire shapes, wire shaping is mostly considered to be impractical. In this paper, we tend to present a sensible wire shaping technique to cut back power consumption of interconnect. Nonregular wire shapes are directly implemented on silicon wafer instead of in GDSII throughout design. We have a tendency to gift novel enhancements to existing optical proximity correction (OPC) technology to accurately print nonregular wire shapes. Experimental results show that the post-OPC mask complexities of uniform wire and nonregular wire are comparable. With minimal impact on the design and producing flows and minimal additional style and producing costs, we have a tendency to demonstrate that wire shaping can help to get substantial reduction of interconnect dynamic power without affecting timing closure. Our wire shaping methodology is a superb example of Producing for Style.
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