Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding


This temporary proposes an occasional-complexity 1st-two-minimum-values generator for a small amount-serial scheme. Since the hardware complexity of generators utilizes a significant portion of the min-total low-density parity-check decoder, a coffee-complexity generator is crucially necessary. To scale back hardware complexity, an existing bit-serial generator that finds only one minimum value rather than two has been proposed; but, it will cause bit error rate (BER) degradation. By contrast, the proposed low-complexity bit-serial generator will notice the precise 1st 2 minimum values and thus can improve the BER performance. Moreover, the proposed generator will not suffer from any throughput loss since its latency is nearly the identical as that of the prevailing generator.

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