Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance


This brief presents a design strategy for spin-transfer torque (STT)-RAM to scale back the error-tolerance redundancy overhead and increase effective storage capability without sacrificing its reliability. The secret is to cohesively exploit the run-time knowledge characteristics (e.g., access unit length and access frequency) and the fundamental browse disturbance versus sensing error tradeoff in STT-RAM. It presents 3 specific data-dependent error-tolerance style techniques, and demonstrates their effectiveness in the context of using STT-RAM to exchange DRAM in solid-state drives. Based on detailed modeling/simulations down to twenty two-nm node, we showed that these style solutions can increase the effective STT-RAM storage capacity by twenty sixpercent, compared with standard design practice.

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